In a typical integrated circuit memory, memory cells are located at intersections of word lines and bit line pairs. A row decoder activates one word line, and memory cells located on the activated word line provide their contents to corresponding bit line pairs. Then column decoding selects at least one bit line pair. A selected memory cell is located at an intersection of an activated word line and a selected bit line pair. During a read cycle, a selected bit line pair is coupled to a data line pair. A sense amplifier detects the contents of the selected memory cell on the data line pair and provides it to global data line pairs as a differential current. A global data line load converts the differential current into a differential voltage and provides the differential voltage to an output buffer for subsequent output.
During the read cycle, the memory couples a given number of bit line pairs, based on row and column decoding, onto corresponding global data line pairs. The given number determines, in part, the organization of the memory. For example, a memory which provides the contents of eight memory cells onto global data line pairs and subsequently outputs the values on the eight global data line pairs has a by-eight (X8) organization. In many commercial applications, however, different organizations are required. For example, applications may require by-four (X4) or by-one (X1) organizations. In order for the memory to provide these different organizations without requiring significant redesign, one or more additional address signals are used to further decode the memory cells selected by row and column decoding. This function is referred to as multiplexing. After multiplexing, the data signals are provided externally to the memory.
Static random access memories designed as integrated circuits require increasingly shorter access times to stay commercially competitive. Shorter access times present difficulties, however. In the case of a memory with a given organization which is adapted to provide a different organization through a multiplexer, the multiplexer significantly delays development of the global data line voltages and increases access time of the memory.